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Features
* * * * * * *
10-bit Resolution 1.5 Gsps Sampling Rate Selectable 1:2 or 1:4 Demultiplexed Output 500 mVpp Differential 100 or Single-ended 50 Analog Input 100 Differential or Single-ended 50 Clock input LVDS Output Compatibility Functions: - ADC Gain Adjust - Sampling Delay Adjust - 1:4 Demultiplexed Simultaneous or Staggered Digital Outputs - Data Ready Output with Asynchronous Reset - Out-of-range Output Bit (11th Bit) * Power Consumption : 6.5W * Power Supplies: -5V, -2.2V, 3.3V and VPLUSD Output Power Supply * Package - Cavity Down EBGA 317 (Enhanced Ball Grid Array) - 25 x 35 mm Overall Dimensions
10-bit 1.5 Gsps ADC With 1:4 DMUX AT84AS003 Summary
Performances
* * * 3 GHz Full-power Analog Input Bandwidth 0.4 dB Gain Flatness from DC up to 1.5 GHz Single-tone Performance at Fs = 1.5 Gsps, Full Nyquist Zone - - * - - ENOB = 8.0 Effective Bits, FIN = 750 MHz SNR = 52 dB, SFDR = -60 dBFS, FIN = 750 MHz Fin1 = 745 MHz, Fin2 = 755 MHz: IMD3 = -60 dBFS Fin1 = 1244 MHz, Fin2 = 1255 MHz: IMD3 = -60 dBFS
Dual-tone Performance (IMD3) at Fs = 1.5 Gsps (-7 dBFS each tone)
Screening
* Temperature Range: - - TC > 0C; TJ < 90C (Commercial "C" Grade) TC > -20C; TJ < 110C (Industrial "V" Grade)
Applications
* * * * * * Direct RF Down Conversion Ultra Wide Band Satellite Receivers Radars and Countermeasures High-speed Acquisition Systems High Energy Physics Automatic Test Equipment
Description
The AT84AS003 combines a 10-bit 1.5 Gsps analog-to-digital converter with a 1:4 DMUX, designed for accurate digitization of broadband signals. It features 8.0 Effective Number of Bits (ENOB) and -60 dBFS Spurious Free Dynamic Range (SFDR) at 1.5 Gsps over the full first Nyquist zone.
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This is a summary document. A complete document is not available at this time. For more information, please contact your local Atmel sales office.
The 1:4 demultiplexed digital outputs are LVDS logic compatible, allowing easy interfacing with standard FPGAs or DSPs .The AT84AS003 operates at up to 1.5 Gsps, without additional tuning of the synchronization between the ADC and DMUX. The AT84AS003 comes in a 25 x 35 mm EBGA317 package. This package has the same TCE as FR4 boards, offering excellent reliability when subjected to large thermal variations.
Figure 1. Block Diagram
BIST ASYNRST PGEB DRRB SDA
2
CLK/CLKN
SDA
20 2 20
Port A AOR/AORN Port B BOR/BORN Port C COR/CORN Port D DOR/DORN DR/DRN
LVDS Buffers
Logic Block
Quantizer
2 20 2 20 2 2
VIN S/H VINN
Demultiplexer 1:2 or 1:4
GA B/GB SLEEP STAGG RS DRTYPE
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AT84AS003
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AT84AS003
Functional Description
The AT84AS003 is a 10-bit 1.5 Gsps ADC combined with a high-speed demultiplexer (DMUX) used to lower the LVDS output bit stream (10-bit data and one out-of range bit) by a factor of 2 or 4. The ADC works in fully differential mode from the analog input to the digital outputs. It provides an on-chip 100 differential termination for the clock input. The analog input is 500 mVpp on a 100 differential input impedance. 50 reverse terminations are required for the analog input. They should be placed as close as possible to the EBGA package input pins (2 mm maximum). The output clock and the output data are LVDS compatible (100 differentially terminated). The AT84AS003 ADC features two asynchronous resets: * * DRRB, which ensures that the first digitized data corresponds to the first acquisition ASYNCRST, which initializes the DMUX
The gain control pin GA is used to finely adjust the ADC gain to a unity gain. The control pin B/GB is provided to select either a binary or gray data output format. A Sampling Delay Adjust function (SDA, activated via the SDAEN signal) may be used to fine-tune the ADC aperture delay by approximately 120 ps around its nominal value. This function is useful when interleaving multiple ADCs. The control pin B/GB is provided to select either a binary or Gray data output format. A tunable delay cell (controlled via CLKDACTRL) is integrated between the ADC and the DMUX on the clock path to fine-tune the data according to the clock alignment at the interface between the ADC and the DMUX. This delay can be tuned from -250 to 250 ps around a default center value, featuring a 500 ps typical tuning range. No tuning should be necessary for operating frequencies up to 1.5 Gsps. An extra stand-alone delay cell is also provided. It is controlled via analog DACTRL control input and activated via DAEN. The tuning range is typically 500 ps. A pattern generator (PGEB) is integrated in the ADC block for debugging purposes or acquisition setup. Similarly, a Built-in Self Test (BIST) is provided for quick debug of the DMUX block. The demultiplexer ratio can be selected using RS (1:2 or 1:4 ratio). Two modes for the output clock (via DRTYPE) are selectable: * * DR mode: only the output clock's rising egde is active, the output clock rate is the same as the output data rate DR/2 mode: both the output clock's rising and falling edges are active, the output clock rate is half the output data rate Staggered: even and odd bits are output with half a data period delay Simultaneous: even and odd bits are output at the same time
The AT84AS003's data is output in two different modes: * *
A sleep mode is provided to lower the power consumption of the DMUX block. Die junction temperature monitoring is also provided to facilitate management of the junction temperature, by sensing the voltage drop across two diodes implemented on the ADC and DMUX respectively, close to the chip's hot point. The AT84AS003 is delivered in an Enhanced Ball Grid Array (EBGA). Its TCE, which is similar to that of the FR4 material, makes it highly suitable for applications exposed to large thermal variations.
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Table 1. Description of Functions
Name VCCA VCCD VEE VMINUSD VPLUSD AGND DGND CLK, CLKN VIN, VINN DRRB ASYNCRST DR/DRN A0...A9 A0N...A9N AOR, AORN B0...B9 B0N...B9N BOR, BORN C0...C9 C0N...C9N COR, CORN D0...D9 D0N...D9N Function Analog 3.3VV power supply Digital 3.3V power supply Analog -5V power supply Digital -2.2V power supply Output 2.5 power supply Analog ground Digital ground Input clock signals Analog input data ADC reset DMUX asynchronous reset Output clock signals Output data port A Additional output bit port A Output data port B Additional output bit port B Output data port C Additional output bit port C Output data port D Name DOR, DORN RS CLKDACTRL DACTRL DAEN DAI, DAIN DAO, DAON GA SDA SDAEN PGEB B/GB SLEEP STAGG CLKTYPE DRTYPE BIST DIODE ADC DIODE DMUX Function Additional output bit port D DMUX ratio selection signal Control signal for clock delay cell Control signal for standalone delay cell Enable signal for standalone delay cell Input signals for standalone delay cell Output signals for standalone delay cell ADC gain adjust ADC sampling delay adjust ADC SDA enable ADC pattern generator Binary or gray output code selection Sleep mode selection signal Staggered mode selection for data outputs Input clock type selection signal Output clock type selection signal Built-in self test Diode for die junction temperature monitoring (ADC) Diode for die junction temperature monitoring (DMUX)
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AT84AS003
Figure 2. Device Pinout
VCCA VEE VMINUSD VCCD VPLUSD
3.3V
-5V -2.2V 3.3V 2.5V 20 2 20 2 20 2 AT84AS003
2 VIN, VINN CLK, CLKN DRRB ASYNCRST SDAEN SDA GA PGEB B/GB DACTRL CLKDACTRL DAI, DAIN SLEEP STAGG CLKTYPE RS DAEN BIST DRTYPE 2
[A0...A9] [A0N...A9N] AOR, AORN [B0...B9] [B0N...B9N] BOR, BORN [C0...C9] [C0N...C9N] COR, CORN [D0...D9] [D0N...D9N] DOR, DORN DR, DRN DAO, DAON DIODE ADC DIODE DMUX
2 2
20 2 2 2
AGND
DGND
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Package Information
Figure 3. EBGA 317 Package Outline (Bottom View)
25 mm
35 mm
25 mm
35 mm
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AT84AS003
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AT84AS003
Ordering Information
Part Number AT84XAS003TP
Package EBGA 317
Temperature Range Ambient Commercial "C" TC > 0C; TJ < 90C Industrial "V" TC> -20C; TJ < 110C Ambient
Screening Prototype
Comments Prototype version Please contact your local Atmel sales office
AT84AS003CTP AT84AS003VTP AT84AS003TP-EB
EBGA 317 EBGA 317 EBGA 317
Standard Standard Prototype Evaluation kit
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5403AS-BDC-10/04

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